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Old 02.10.2006, 19:44   #1
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Question Java Verilog Parser

интересует Verilog grammar
что то наподобие http://pyparsing.wikispaces.com/WhosUsingPyparsing
но это сделан с помощью pyparsing Python module
у кого что интереснее есть или знает где искать
нужен для digital cirucit simulator-а
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Old 02.10.2006, 20:31   #2
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ne google-lil? esli na jave ne naidetsya, na C++ ix navernyaka kucha... mojesh perevesti na javu sam, ili swigom (swig.org).
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Old 02.10.2006, 20:43   #3
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de bekus-nauri formen ka, mnac grel@
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Old 03.10.2006, 09:51   #4
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merci zhoxovurd
antlr parser generator ov erevi anem mech lik@ petkakan baner uni
xotja iranc verilog grammar@ mec netlist neri hamar dzhvar karanam ogtagorcem
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Old 03.10.2006, 12:53   #5
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a v gotovix productax Synopsys-a ili XILINX takix parserov netu? mojno tam poshupat
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Old 03.10.2006, 13:12   #6
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jest spice-i synopsys ovskije eldo verilog simulatori i procheje no mne snachala na urovne prostejshix gate-ov nada *deadline 20 oct* - xochu chto porposhe event driven sdelat zapixnut vsjo v queue of gates i pri value change e algorithmom proverjajet kakoi iz gate ov imejet podxodjashije znachenija nu i potom uzhe simulirovat ..
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