Join Date: 08 2004
Location: London, UK
Reputation: 482 | 7
| | Are ASICs dead?
| Q: Are ASICs dead? |
Kish: According to Gartner, it was about a $23 billion market last year, and in the period from 2002 to 2010 it’s growing a little bit faster than the overall semiconductor market. So why are we debating whether the ASIC market will survive when it’s going up and to the right? I substituted another question in there, ‘What is an ASIC?’ An ASIC these days is a thinly veiled ASSP. It probably started life as an ASSP platform, like OMAP, which then has been adapted by a vendor like TI for an application that’s very specific like cell phones and based on a technology that they have a leadership position in, like DSP. If you have all of those conditions, you can have a pretty nice start to ASIC development. Why? Because the burden shifted from the system vendor to the chip vendor for having hard-wired features on a board. What happens is ASSPs become demo chips. Low-volume users adopt them directly. High-volume users go back and negotiate with those powerful semiconductor players to get them adapted to their specific value proposition. This model is working very well.
Carlson: The original model for ASICs is dying a slow and painful death, but we’ve given birth to several new models. We’re going through this transition as a result of trying to cope with the tradeoffs between the various models available to design teams. There are huge jaws crushing ASICs, on the programmable side and the ASSPs. On top of that, the technology foundation is in flux and constantly getting more complicated and so is the programmability, from the software side. Through these formulations of disaggregation, it’s interesting to look at the value chain in terms of margins and tradeoffs between the physical aspects of the chip—performance, area and power—and also time to market. What’s not being managed in this process are margins. That’s not just profits. It’s design margins. There turns out to be a very profound impact to one-size-fits-all designs.
Massabki: ASICs don’t need saving. It’s a very large market with a number of segments. There are full custom ASICs, standard cell ASICs, embedded arrays, structured ASICs and also gate arrays. The dynamics are different for each of these. Some are declining, some are growing. In 2000, companies began to shrink their budgets and ASICs took a big hit. That was a big drawback to innovation, and innovation was replaced by risk mitigation. ASIC design excellence, in general, suffered. In the past few years there have been new technologies to address risk mitigation, time to market and cost, such as structured ASICs and the latest versions of embedded arrays. Those have been a little bit slow to adopt. The real question is, ‘What will drive growth?’” Companies typically use ASICs early in a lifecycle when there are no standard products out there and they want to add their own innovation and be first to market. You need emerging markets and innovation. We’re also starting to see the financial health of ASIC companies get better, so design starts are increasing.
Durden: Historically, an ASIC has been a custom chip done by a system OEM to add value into their system. There is a lot of evidence that is in decline. System OEMs have had a difficult time justifying the expense and risk of developing those custom solutions and instead are relying more and more on standard products. They’re shifting the risk of developing those products to semiconductor companies. It’s simple economics. The cost of developing a custom chip is tens of millions of dollars. To get a return on that development you’ve got to have a very large business to support it. It’s therefore difficult for any one system OEM versus a semiconductor company, which can develop it for a number of customers and amortize the cost. There’s been talk that the real issue is the difficulty of developing an ASIC and the rising cost of mask sets, and that FPGAs and structured ASICs are the solution. I would say that’s not the case because only a small percentage of the cost of developing a chip is going into the cost of implementing it in silicon. The rest of the expense is defining the architecture, designing it, verifying it, and implementing all the software that runs of the chip…In terms of the total market, it’s a $20 billion market for ASICs and another $60 billion for ASSPs. It’s a very large market and it’s growing.
Sherwani: The question I would like to ask is, ‘Why have ASICs survived?’ They didn’t deserve to—ridiculous cost, extremely unpredictable, extremely unreliable. Traditional ASIC vendors did everything in their power to kill it. If you were running a container business that way, there would be no containers shipped in the world today. You know why they survived? They survived because they were needed. At the end of the day, hardware differentiation is what differentiates one company from another. You can never do in software what you can do in hardware. You can do magic with transistors. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing. If we can make them cost effective, predictable and reliable, a lot more people will build ASICs. We need design discipline. Do you know how many standards there are? Do we need them? Open Silicon is dealing with 475 packages. Does the world need 475 packages?
Q: Is there a sweet spot for custom silicon?
Kish: If there is some segment of that die that is programmable while other major functions are fixed, you end up with a solution that is both software programmable and hardware programmable on the same chip. You can serve multiple applications.
Carlson: There are an incredible variety of designs that I see. When we’re talking about discipline and uniformity, there’s a very good reason why each one has something a little bit different. Because the tradeoffs are so complicated, there’s definitely good reason for that. Custom is an area where you’re taking more risk. Not everyone’s a market leader, but everyone aspires to be one.
Massabki: Architecture is key. More integration is not necessarily the right solution. What do you do when you have a chip with 20 million gates and you want to add more? You can just imagine how long it takes to re-spin that design. A smart architecture, where you have a fixed functionality that doesn’t change and something next to it that does, is better than having a single chip that’s fully integrated. It doesn’t necessary need to be programmable, but it needs to be small enough that it can be re-spun quickly. That way not everyone has to pay the cost of building a fully integrated chip.
Durden: The least expensive chip we sell is 40 cents, and the most expensive is $400, so there are three orders of magnitude between them. In the past, everyone moved regularly from node to node. Now some people are hanging back while others are moving forward, so it’s hard to define the sweet spot. Anything that you can do to add unique capability to your chip is the sweet spot, whether that’s an analog capability or a particular digital algorithm or programmability. But you need to do it in a way that allows you to get an adequate return on that differentiation.
Sherwani: There are three or four different segments. People are often building an ASSP, but at the beginning there is not enough volume. In the first three or four years we will build a chip, then a company like Marvell or Broadcom will come into the market and kill it and take it over. That is one sector. Those chips are typically made by startups. We call them introduction-to-ASSP-market chips. Not all of them survive. They fall in all of those categories mentioned so far. It is not about the type of chip. It is about time to market. The second kind of business is one where the volume is not there and will never be there because it is a niche market. A third business has to do with fleeting markets. Standards are changing and you have an availability of market for two years. Broadcom and Marvell are not participating because they don’t move fast enough. It’s moored not by the technology but by the time to market.
Q: There’s a trend to outsource basic R&D and development. How will that affect the ASIC business?
Sherwani: That was a very good question. We have predicted that for seven to eight years. In-house development is very expensive. We are seeing two things. One is outsourcing, one is offshoring. Many people are setting up their own facilities in other countries. Others are outsourcing. That will allow companies like Cypress to use their headcount on the leading-edge design, which is where they should be, and the re-spin designs can be done by outsourcing or offshoring. In North America, trying to do some of those re-spin designs is very expensive.
Carlson: It’s been quite a while since the semiconductor industry has used process technology as a form of differentiation. In the early days of LSI vs. VLSI, it was how many transistors can you put on a chip? Bigger was better. Over the past decade you’ve seen a lot more with IP. That will continue. Services has long been an area of importance. And price is important. What people haven’t done yet is execute on power. There are a huge variety of solutions in the custom space that haven’t been deployed in the ASIC market. The first movers there are going to enjoy some advantage for a period of time.
Durden: It’s finally gotten to the point where a company like TI or NXP can no longer afford the capital investment of the fab and then fill the fab. The differentiation is not so much at the process technology these days. As to how it applies to the ASIC business, it’s good for us. The more people that use industry standard processes, the more IP that’s going to be available on those processes. That will make it easier and easier to develop custom chips.
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