IC Nanometer Design Technical Publication Listing
* IEEE Std VHDL 1076.1-1999: The Analog and Mixed-Signal Extensions for VHDL
* CD Dispersion Across the Lens Field: Influence on Transitor Characteristics
* Microlithography Cost Analysis - Presented at Interface '99 Symposium
* Interconnect Simple: Accurate and Statistical Models Using On-Chip Measurements for Calibration
* Circuit Simulation for DSM IC Power Analysis
* Achieving DSM Timing Closure with TeraPlace, a Physical Optimization Solution
* A New Process Monitor for Reticles and Wafer
* Phase Aware Proximity Correction for Advanced Masks
* OPC beyond 0.18 mm: OPC on PSM Gates
* Implementation Issues for Production OPC
* Full-chip Process Simulation for Silicon DRC
* Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs
* Verification of Radio-Frequency Transceivers
* Noise Considerations in Circuits and Systems
* VCO Simulations with Eldo RF (tuning range and phase noise)
* TICER: Realizable Reduction of Extracted RC Circuits
* Experimental Results on Optical Proximity Correction with Variable Threshold Resist Model
* Sub-resolution process windows and yield estimation technique based on detailed full-chip CD Simulation
* Verifiable Optical Proximity Correction (OPC) Methodologies
* Effects of Advanced Illumination Schemes on Design Manufacturability and Interactions with Optical Proximity Corrections
* Implementation of Hot-Carrier Reliability Simulation in Eldo
* Sun Compute Farms for Electronic Design
* Sun Technical Compute Farm (Sun TCF)
* Achieving Greater Capacity for Physical Verification without Losing Performance
* Common Rail Injection System described in VHDL-AMS and Simulated with ADVance MS
* Mixed-Signal ASIC Top-Down and Bottom-Up Design Methodologies using VHDL-AMS
* Validation of a New Methodology using VHDL-AMS on a Hard-disk Drive Design
* A unified approach of PM noise cancellation in large RF multitone autonomous circuits
* Correction For Etch Proximity: New Models and Applications
* 64-bit resolution enhancement technologies improve sub-wavelength silicon accuracy, speed, and yield
* Fully Automatic Side Lobe Detection and Correction Technique for Attenuated Phase Shift Masks
* (Sub-) 100nm Gate Patterning Using 248nm Alternating PSM
* Impact of RET on Physical Layouts
* Modeling of Timing Jitter in Oscillators
* Efficient Algorithm for Steady-State Stability Analysis of Large Analog-RF Circuits
* Simulation Method to Extract Characteristics for Digital Wireless Communication Systems
* LVS Automatic Test Vehicles
* Cambio: Interactive compaction of mixed signal layout with the IC Station
* Using Calibre in a Design for Manufacturability Environment
* The Physical Verification Challenge - Mentor Graphics and Sun Microsystems Partnership Success Story
* Adjustment of Optical Proximity Correction (OPC) Software For Mask Process Correction (MPC)
* MEEF as a Matrix
* Hierarchical GDSII-based fracturing and job deck system
* Port Impedance and Admittance Modeling Using Eldo and Eldo RF
* A Streamlined Approach for Debugging LVS Errors
* Partnering For Effective Ruledeck Creation
* Circuit Simulation for Full-Chip SoC Designs
* Eliminating the Problems of Dual Physical Verification Flows
* Is Silicon "Free"?
* Model Assisted Double Dipole Decomposition
* RET Compliant Cell Generation for sub-130nm Processes
* Contrast-Based Assist Feature Optimization
* Overcoming Physical Verification Challenges In a 100-million+--Transistor SoC Design
* Universal Process Modeling with VTRE for OPC
* Design Verification Flow for Model Assisted Double Dipole Decomposition
* Model-Based OPC Considering Process Window Aspects - A Study
* Streamlining the SoC Design Flow
* Design Capture for Analog-Mixed-Signal SoCs-It's Not Just About Entering Schematics Anymore!
* Inductor Device Generators for Automation of RF IC Design
* A GDS-based Mask Data Preparation Flow - Data Volume Containment by Hierarchical Data Processing
* Alternatives to Alternating Phase Shift Masks for 65nm
* Complementary Double Exposure Technique (CODE), solutions for the two dimensional structures of the 90nm node
* Design Integrity Issues affecting mixed-signal designs
* The Glue in a Confident SoC Flow
* LVS - Parasitic Extraction Link: Why Stronger is Better
* Measuring Physical Parameters: Make Assumptions, Make Mistakes
* Optimization of the Data Preparation for Variable Shaped Beam Mask Writing Machines
* Statistical Data Assessment for Optimization of the Data Preparation and Manufacturing
* Model-Assisted Placement of Sub-resolution Assist Features: Experimental Results
* New Process Models for OPC at sub-90nm Nodes
* New Stream Format: Progress Report on Containing Data Size Explosion
* MDP in a Nutshell: Understanding Mask Data Preparation
* Staying Competitive: Advantages of Adopting a Single Tool for AMS SoC
* Bluetooth Transceiver Design with VHDL-AMS
* Integration of OPC and Mask Data Preparation
* High performance fracturing for variable shaped beam mask writing machines
* Design Strategies for Future Lithographic Technologies (or, OPC will never die)
* Power Amplifier Simulations with Eldo RF(ACPR)
* Addressing the Layout Challenges of Increasing Analog Content in SoCs
* Introduction to ADMS RF (Digital AGC Loop)
* Using the CODE technique to print complex two-dimensional structures in a 90nm ground rule process
* Confronting the Challenges of Nanometer Design
* Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning
* Beyond P-Cell and Gate-Level Assumptions: Accuracy Requirements for Simulation of Nanometer Designs
* Challenges of Silicon Modeling in Nanometer Designs
* Methodology Shift: Adopting a Design for Manufacture Flow
* The Necessary Link for Design Closure: LVS-Parasitic Extraction
* Shifting Methods: Adopting a Design for Manufacture Flow
* Resistance Matrix in Crosstalk Modeling for Multiconductor Systems
* OASIS - based data preparation flows: Progress report on containing data size explosion
* Combining OPC and design for printability into 65nm logic designs
* Critical failure ORC - Application to the 90-nm and 65-nm nodes
* New Concepts in OPC
* Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future
* DFM: Magic Bullet or Marketing Hype
* Evaluation of IDEALSmile for 90[nm] FLASH memory contact holes imaging with ArF scanner
* DFM: What is it and what will it do?
* Calibration of OPC models for multiple focus conditions
* Interaction of RET and MDP: Optimization for reducing the mask writing time
* Detailed Process Analysis for Sub-Resolution Assist Features Introduction
* Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs
* An agile mask data preparation and writer dispatching approach
* Parasitic Effects, Nanometer Silicon Modeling and Calibre xRC
* Benefits of Outsourcing Rule Decks
* Calibre MTflex: Reducing the High Cost of Processing Power
* OASIS-based unification of mask data representation
* Model-Based Prediction of Full-Chip SRAF Printability
* Electron Transport Through Metal-Multiwall Carbon Nanotube Interfaces
* The Platform Solution: Leveraging Calibre's Power of Integrated, High Performance Tools
* An Agile Mask Data Preparation and Writer Dispatching Approach
* Analog IP Migration Using Design Knowledge Extraction
* A Fully Automated Approach for Analog Circuit Reuse
* Benefits of Outsourcing Rule Decks
* The Need for Advanced Silicon Modeling in RF Nanometer Designs
* Challenges to Silicon Modeling in the Nanometer Era
* Design for Manufacturing: What Designers Need to Know About the Change in Yield Management
* Advanced Methods for Chip Finishing in Large Nanometer Designs
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IC Nanometer Design > Technical Publications
